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W78C438C 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C438C is a high-performance single-chip CMOS 8-bit microcontroller that is a derivative of the W78C58 microcontroller family. The W78C438C is functionally compatible with the W78C32, except that it provides either a 64 KB program/1 MB data memory address or memory-mapped chip select logic, five general I/O ports, and four external interrupts. In the W78C32, two I/O ports, Port 1 and Port 3, are available for general-purpose use (Port 3 also supports alternative functions), and Port 2 and Port 0 are used as the address bus and data bus, respectively. To enable Port 0 and Port 2 to also be used as general purpose I/O ports, the W78C438C provides two dedicated address ports (AP5 and AP6) that serve as address output for 64 KB of memory and one address/data port (DP4) that serves as ROM code input and external RAM data input/output. Unlike the W78C32, this product does not require an external latch device for multiplexing low byte addresses. The W78C438C also provides four pins (AP7.0-AP7.3) to support either 64 KB program/1 MB data memory space or memory-mapped chip select logic, one parallel I/O port (Port 8) without bit addressing mode, and two additional external interrupts (INT2 , INT3 ) . The W78C438C is programmed in a manner fully compatible with that used to program the W78C32, except that the external data RAM is accessed by the "MOVX @Ri" instruction. Address paging is performed by loading page addresses into the HB (high byte) register, which is not a standard register in the W78C32, before execution of the "MOVX @Ri" instruction.
FEATURES
* 8-bit CMOS microcontroller * Fully static design * DC to 40 MHz operation * ROM-less operation * 256-byte on-chip scratchpad RAM * Either 64 KB program/1 MB data memory address space or 4 memory-mapped chip select pins * One 8-bit data/address port * Two 8-bit and one 4-bit (optional) address ports * Five 8-bit bidirectional I/O ports
- Four 8-bit bit-addressable I/O ports and one 8-bit parallel I/O port
* Eight-source, two-level interrupt capability * Three 16-bit timer/counters * Four external interrupts * One full-duplex serial channel * Built-in power management
- Idle mode - Power-down mode * Packages: - 84-pin PLCC: W78C438CP-24/40 - 100-pin PQFP: W78C438CF-24/40
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Publication Release Date: July 1998 Revision A1
W78C438C
PIN CONFIGURATIONS
P 1 . 4
P 1 . 3
P 1 . 2
P 1 . 1
D P P 1 4 .N. 0C7
D P 4 . 6
D P 4 . 5
D P 4 . 4
D P 4 . 3
D P 4 . 2
D P 4 . 1
D P 4 V .ND 0CD
P 0 . 0
P 0 . 1
P 0 . 2
P 0 . 3
P 0 . 4
P1.5 P1.6 P1.7 RESET P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 INT3 INT2 RXD, P3.0 VDD TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11987654 10
32188888 43210
77777 98765
W78C438CP
84-pin PLCC
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
P0.5 P0.6 P0.7 EA AP5.0 AP5.1 AP5.2 AP5.3 AP5.4 AP5.5 AP5.6 AP5.7 V DD VSS ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3
333333344444444445555 345678901234567890123
P 3 . 6 , / W R
P 3 . 7 , / R D
X T A L 2
XVNAA T SCPP 77 AS .. L 1 32 ,, // CC SS 32
A P 7 . 1 , / C S 1
A P 7 . 0 , / C S 0
A P 6 . 7
A P 6 . 6
A P 6 . 5
A P 6 . 4
A P 6 . 3
A P 6 . 2
A P 6 . 1
A P 6 . 0
P 2 . 0
P 2 . 1
P 2 . 2
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W78C438C
Pin Configurations, continued
T 2 E X , P 1 . 4 P 1 . 3 P 1 . 2 P 1 . 1
T 2 , P 1 . 0 D P 4 . 7 D P 4 . 6 D P 4 . 5 D P 4 . 4 D P 4 . 3 D P 4 . 2 D P 4 . 1 D P 4 . 0 V D D P 0 . 0 P 0 . 1 P 0 . 2 P 0 . 3
N C
N C
NC NC NC NC P1.5 P1.6 P1.7 RESET P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 INT3 INT2 RXD, P3.0 VDD TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 0 0
9 9
9 8
9 7
9 6
9 5
9 4
9 3
9 2
9 1
9 0
8 9
8 8
8 7
8 6
8 5
8 4
8 3
8 2
8 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC NC NC P0.4 P0.5 P0.6 P0.7 EA AP5.0 AP5.1 AP5.2 AP5.3 AP5.4 AP5.5 AP5.6 AP5.7 V DD V SS ALE PSEN P2.7 P2.6 P2.5 P2.4 NC NC NC NC P2.3
W78C438CF
100-pin PQFP
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
P 3. 7, / R D
X T A L 2
X T A L 1
V S S
N C
A P 7 . 3 , / C S 3
A P 7 . 2 , / C S 2
A P 7 . 1 , / C S 1
A P 7 . 0 , / C S 0
A P 6 . 7
A P 6 . 6
A P 6 . 5
A P 6 . 4
A P 6 . 3
A P 6 . 2
A P 6 . 1
A P 6. 0
P 2 . 0
P 2 . 1
P 2 . 2
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Publication Release Date: July 1998 Revision A1
W78C438C
PIN DESCRIPTION
P0.0-P0.7 I/O Port 0
These pins function the same as those in the W78C32, except that a multiplexed address/data bus is not provided during accesses to external memory.
P1.0-P1.7 I/O Port 1
Functions are the same as in the W78C32.
P2.0-P2.7 I/O Port 2
Functions are the same as in the W78C32, except that an upper address bus is not provided during accesses to external memory.
P3.0-P3.7 I/O Port 3
Functions are the same as in the W78C32.
DP4.0-DP4.7 Data/Address Bus
DP4 provides multiplexed low-byte address/data during access to external memory.
AP5.0-AP5.7 Address Bus
AP5 outputs the <7:0> address of the external ROM multiplexed with the <7:0> address of the external data RAM.
AP6.0-AP6.7 Address Bus
AP6 outputs the <15:8> address of the external ROM multiplexed with the <15:8> address of the external data RAM. During the execution of "MOVX @Ri," the output of AP6 comes from the HB register, which is the page register for the high byte address, and its address is 0A1H.
AP7.0-AP7.3 Address Bus/Chip Select Pins
Set bit 7 of the EPMA (Extended Program Memory Address) register to determine the functions of port 7. When this bit is "0" (default value), AP7 allows the external memory data to be accessed by outputting the <19:16> address of the external memory from bits<3:0> of the EPMA register during the execution of "MOVC A, @A+DPTR" or "MOVX dest, src." At all other times, AP7<3:0> will output 0H. When this bit is "1," AP7<3:0> (CS3-0) are the chip select pins, which support memory-mapped peripheral device select, and only one pin is active low at any one time. These pins are decoded by AP6<7:6>. For details, see the table below. AP6.7 0 0 1 1 AP6.6 0 1 0 1 DESCRIPTION AP70: low; others: high AP71: low; others: high AP72: low; others: high AP73: low; others: high
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W78C438C
P8.0-P8.7 I/O Port
Functions are the same as those of Port 1 in the W78C31, except that they are mapped by the P8 register and not bit-addressable. The P8 register is not a standard register in the W78C32. Its address is at 0A6H.
INT2 , INT3 External Interrupt, Input
Functions are similar to those of external INT0 , INT1 in the W78C32, except that the functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the W78C32. Its address is at 0C0H. For details, see the Functional Description below.
EA External Address, Input
Functions same as W78C32.
RST, XTAL1, XTAL2, PSEN , ALE
Functions same as W78C32.
BLOCK DIAGRAM
Port 8
SFR
Port 0 Port 1 Alternate
RAM 256 Bytes Data Bus CPU CORE
Timer2 Port 2 Port 3 Alternate Serial Port INT0 Interrupt INT1 Timer0 Timer1 INT2 INT3
DP4 AP5 AP6 AP7 Alternate
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Publication Release Date: July 1998 Revision A1
W78C438C
FUNCTIONAL DESCRIPTION
The W78C438C is a functional extension of the W78C58 microcontroller. It contains a 256 x 8 RAM, 64 KB program/1 MB data memory address or memory-mapped chip select logic, two 8-bit address ports, one 8-bit data port, five general I/O ports, four external interrupts, three timers/counters, and one serial port.
Dedicated Data and Address Port
The W78C438C provides four general-purpose I/O ports for W78C32 applications; the address and data bus are separated from Port 0 and Port 2 so that these ports can be used as general-purpose I/O ports. In this product, DP4 is the data bus for external ROM and RAM, AP5<7:0> are the low byte address, AP6<7:0> are the high byte address, PSEN enables the external ROM to DP4, and P3.6 ( WR ) and P3.7 (RD ) are the write/read control signals for the external RAM. The external latch for multiplexing the low byte address is no longer needed in this product. The W78C438C uses AP5 and AP6 to support 64 KB external program memory and 64 KB external data memory, just as a standard W78C32 does. The W78C438C provides four pins, AP7.3-AP7.0 (CS3-CS0), to support either 64 KB program/1 MB data memory space or memory-mapped chip select logic. Bit 7 of the EPMA (Extended Program Memory Address) register, which is described in Table 1 below, determines the functions of these pins. When this bit is "0" (the default value), AP7<3:0> support external program/data memory addresses up to 64 KB/1 MB for applications which need additional external memory to store large amounts of data. Although there is 1M bytes memory space, instructions stored here can not be run at full range of this area except the first 64 Kbytes. It is owing to the fact that during the instruction fetch cycle, AP7<3:0> always output 0s to address lines A19-A16. This limits the program code to store at address 0- 0FFFFH (64K). The rest of the area (10000H-FFFFFH) can be treated as ROM data storage which can be read by "MOVC A, @A+DPTR" instruction. When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is executed to access the external RAM data, AP7<3:0> output address <19:16> from bits <3:0> of the EPMA (Extended Program Memory Address) register. At other times, AP7<3:0> always output 0H to ensure the instruction fetch is within the 64K program memory address. Different banks can be selected by modifying the content of the EPMA register before the execution of "MOVC A, @A+DPTR" or "MOVX dest, src." [Example]. Access the external ROM/RAM data from external memory space. CLR A ; Clear Accumulator. MOV DPTR, #0H ; Clear DPTR. MOV 0A2H, #02 ; Initialize EPMA(0A2H). EPMA.7 = 0: extended memory space ; EPMA.<3:0> = 0010B, the address range: 20000-2FFFFH. MOVC A, @A+DPTR ; Read the external ROM data from location 20000H. MOVX A, @DPTR ; Read the external RAM data from location 20000H. CLR A MOV 0A2H, #03H ; EPMA.<3:0> = 0011B, the address range: 30000H-3FFFFH. MOVC A, @A+DPTR ; Read the external ROM data from location 30000H. MOVX @DPTR, A ; Write the contents of Accumulator to external RAM data. ; location 30000H. -6-
W78C438C
(A) EPMA.7 = 0
EPROM W78C438
P0 AP5 AP6 P1 P2 PSEN P8 INT0 INT1 INT2 INT3 RD WR P3 OE AP7 DP4 ADDR (20-bit)
\8 \8 \4 \8
64K PROGRAM
DATA AREA
RAM
ADDR 1MB (20-bit) DATA WE OE
When bit 7 of the EPMA is "1," AP7<3:0> are the output pins that support memory-mapped peripheral chip select logic, which eliminates the need for glue logic. These pins are decoded by AP6<7:6>. Only one pin is active low at any time. That is, they are active individually with 16K address resolution. For example, CS0 is active low in the address range from 0000H to 3FFFH, CS1 is active low in the address range from 4000H to 7FFFH, and so forth. (B) EPMA.7 = 1
EPROM
64K PROGRAM
W78C438
P0 AP5 AP6 P1 DP4 P2 PSEN P8 INT0 INT1 INT2 INT3 P3 AP7.0 AP7.1 AP7.2 AP7.3
ADDR (16-bit)
\8 \8 \8
DATA AREA
OE
\8 \6
RAM
ADDR (14-bit) 0000h DATA 3FFFh (16k)
Device Device Device 4000h 7FFFh (16k) (16k) (16k) 8000h BFFFh C000h FFFFh
RD WR
WE OE
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Publication Release Date: July 1998 Revision A1
W78C438C
The EPMA register is a nonstandard 8-bit SFR at address 0A2H in the standard W78C32. To read/write the EPMA register, one can use the "MOV direct" instruction or "read-modify-write" instructions. Bits <6:4> of the EPMA register are reserved bits, and their output values are 111B if they are read. The content of EPMA is 70H after a reset. The EPMA register does not support bitaddressable instructions. BIT 7 6 5 4 3 2 1 0 NAME EPMA7 EPMA6 EPMA5 EPMA4 EPMA3 EPMA2 EPMA1 EPMA0 FUNCTION EPMA7 = 0: 64 KB program/1 MB data memory space mode EPMA7 = 1: memory-mapped chip select mode Reserved Reserved Reserved Value of AP7.3 Value of AP7.2 Value of AP7.1 Value of AP7.0
Table 1. Functional Description of EPMA Register
Additional I/O Port
The W78C438C provides one parallel I/O port, Port 8. Its function is the same as that of Port 1 in the W78C31, except that it is mapped by the P8 register and is not bit-addressable. The P8 register is not a standard register in the standard W78C32. Its address is at 0A6H. To read/write the P8 register, one can use the "MOV direct" instruction or "read-modify-write" instructions. [Example]: MOV MOV 0A6H, A A, 0A6H ; Output data via Port 8. ; Input data via Port 8.
Additional External Interrupt
The W78C438C provides two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupts 0 and 1 in the W78C32. The functions (or the status) of these interrupts are determined by (or shown by) the bits in the XICON (External Interrupt Control) register. For details, see Table 2. The XICON register is bit-addressable but is not a standard register in the standard 80C32. Its address is at 0C0H. To set/clear the bit of the XICON register, one can use the "SETB(CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. The interrupt vector addresses and the priority polling sequence within the same level are shown in Table 3. [Example]. SETB SETB SETB CLR 0C0H 0C3H 0C2H 0C4H ; INT2 is falling-edge triggered. ; INT2 is high-priority. ; Enable INT2 . ; INT3 is low-level triggered.
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W78C438C
BIT 7 6 5 4 3 2 1 0
ADDR. 0C7H 0C6H 0C5H 0C4H 0C3H 0C2H 0C1H 0C0H
NAME PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
FUNCTION High/low priority level for INT3 is specified when this bit is set/cleared by software. Enable/disable interrupt from INT3 when this bit is set/cleared by software. If IT3 is "1," IE3 is set/cleared automatically by hardware when interrupt is detected/serviced.
INT3 is falling-edge/low-level triggered when this bit is set/cleared by software.
High/low priority level for INT2 is specified when this bit is set/cleared by software. Enable/disable interrupt from INT2 when this bit is set/cleared by software. If IT2 is "1," IE2 is set/cleared automatically by hardware when interrupt is detected/serviced.
INT2 is falling-edge/low-level triggered when this bit is set/cleared by software.
Table 2. Functions of XICON Register
INTERRUPT SOURCE External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3
VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH 33H 3BH
Table 3. Priority of Interrupts
PRIORITY SEQUENCE 0 (Highest) 1 2 3 4 5 6 7 (Lowest)
Newly Added Special Function Registers
The W78C438C uses four newly defined special function registers, which are described in Table 4. To read/write these registers, use the "MOV direct" or "read-modify-write" instructions.
REGISTER ADDR. FUNCTION LENGTH R/W TYPE R/W R/W VALUE AFTER RESET 00H 70H
1 2
HB EPMA
A1H A2H
During the execution of "MOVX @Ri," the content of HB is output to AP6. EPMA.7 determines functions of AP7. EPMA.3-EPMA.0 determine values of AP7<3:0> when EPMA.7 is "0." The content of P8 is output to port 8. The bits of XICON determine/show the functions/status of INT2 - INT3 . Bit-addressable. Table 4. Newly Added Special Function Registers of the W78C438C
8 8
3 4
P8 XICON
A6H C0H
8 8
R/W R/W
0FFH 00H
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Publication Release Date: July 1998 Revision A1
W78C438C
Notes: 1. The instructions used to access these nonstandard registers may cause assembling errors with respect to the 2500 A. D. assembler, but these errors can be ignored by adding directive ".RAMCHK OFF" ahead these instructions. 2. In the newly added SFR of W78C438C, only XICON register is bit-addressable.
Power Reduction Function
The W78C438C supports power reduction just as the W78C32 does. The following table shows the status of the external pins during the idle and power-down modes. FUNCTION Idle Power Down ALE, PSEN 11 00 P0-P3, P8 Port Data Port Data DP4 Floating Floating AP5, AP6 Address Address AP7 Note Note
Note: AP7 is either 0 or a value decoded by AP6<7:6>, depending on the value of EPMA.7.
Programming Difference
The W78C438C is programmed in the same way as the W78C32, except that the external data RAM is accessed by a "MOVX @Ri" instruction. To support address paging, there is an additional 8-bit SFR "HB" (high byte), which is a nonstandard register, at address 0A1H. During execution of the "MOVX @Ri" instruction, the contents of HB are output to AP6. The page address is modified by loading the HB register with a new value before execution of the "MOVX @Ri" instruction. To read/write the HB register, one can use the "MOV direct" instruction or "read-modify-write" instructions. The HB register does not support bit-addressable instructions. [Example]. MOV MOV MOVX MOV MOVX R1, #0H A, @R1 0A1H, #12H @R1, A ; R1 = 0. ; Read the contents of external RAM location FF00H into ; Accumulator. ; HB contents 12H. ; Copies the contents of Accumulator into external RAM ; location 1200H.
0A1H, #0FFH ; HB contents FFH.
ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VDD-VSS VIN TOPR TSTG MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VDD +0.3 70 +150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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W78C438C
DC CHARACTERISTICS
VDD-VSS = 5V 10%, TA = 25 C, FOSC = 20 MHz, unless otherwise specified.
PARAMETER Oper. Voltage Oper. Current Idle Current Pwdn Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Input Voltage Input Voltage Input Voltage Input Voltage Input Voltage Input Voltage
Notes:
SYM. VDD IDD IIDLE IPWDN ILK1
TEST CONDITIONS * No load Program idle mode Program power-down mode
INT2 , INT3
MIN. 4.5 -300
TYP. 5 -
MAX. 5.5 20 7 50 +10
UNIT V mA mA A A A A A V V V V V V V V V V V V
Internal pull-high ILK2 ILK3 ILK4 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 VILT VIHT VILC VIHC VILR VIHR RESET Internal pull-low EA , Port 0, DP4 P1, P2, P3, P8 IOL1 = 2 mA
Notes 1, 2
-10
Notes 1, 2 Note 1 Note 1
-
+300 +10 +10 0.45 0.45 0.45 0.8
Note 4
-10 -50 2.4 2.4 2.4 0 2.4
(Port 1, 2, 3, 8)
IOH1 = -100 A (Port 1, 2, 3, 8) IOL2 = 4mA (ALE, PSEN, P0, DP4) IOH2 = -400 A (ALE, PSEN, P0, DP4) IOL2 = 2 mA VDD = 5V 10% VDD = 5V 10% VDD = 5V 10%, XTAL1 VDD = 5V 10%, XTAL1 VDD = 5V 10%, RESET VDD = 5V 10%, RESET
Note 5 Note 5 Note 5 Note 5 Note 3
Note 3
(AP5, AP6, AP7)
IOH2 = -100 A (AP5, AP6, AP7)
0 3.5 0 2.4
0.8
Note 4
0.8
Note 4
1. 0 < VIN < VDD, for INT2 , INT3 , RESET, EA , Port 0, DP4, P1, P2, P3 and P8 inputs in leakage. 2. Using an internal pull low/high resistor (approx. 30K). 3. ALE, PSEN , P0 and DP4 in external program or data access mode. 4. The maximum input voltage is VDD +0.2V. 5. XTAL1 is a CMOS input and RESET is a Schmitt trigger input.
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Publication Release Date: July 1998 Revision A1
W78C438C
AC CHARACTERISTICS
AC specifications are a function of the particular process used to manufacture the product, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation.
Clock Input Waveform
PARAMETER Operating Speed Clock Period Clock High Clock Low SYMBOL FOP TCP TCH TCL MIN. 0 25 10 10 TYP. MAX. 40 UNIT MHz nS nS nS NOTES 1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER Address Valid to PSEN Low PSEN Low to Data Valid SYMBOL TAPL TPDV MIN. 2 TCP TYP. MAX. 2 TCP UNIT nS nS
Data Memory Read/Write Cycle
PARAMETER Address Valid to RD Low RD Low to Data Valid Data Hold After RD High RD Pulse Width Address Valid to WR Low Data Valid to WR Low Data Hold After WR High WR Pulse Width SYMBOL TARL TRDV TRDQ TRS TAWL TDWL TWDQ TWS MIN. 4 TCP 0 6 TCP - 4 TCP 1 TCP 1 TCP 6 TCP - TYP. 6 TCP 6 TCP MAX. 4 TCP + 4 TCP 2 TCP 4 TCP + UNIT nS nS nS nS nS nS nS nS
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
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W78C438C
TIMING WAVEFORMS
Program Fetch Cycle
S1 XTAL1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
PSEN TAPL AP6<7:0> AP5<7:0> TPDV DP4<7:0>
address code address
Data Memory Read/Write Cycle
S4 XTAL1 PSEN AP7<3:0>
(When bit7 of EPMA is 0.) addr <19:16> out
S5
S6
S7
S8
S9
S10
S11
S12
S1
S2
S3
AP6<7:0> AP5<7:0>
DPH or HB SFR out
PGM address
DPL or Ri out
PGM address
TARL RD DP4<7:0> WR TAWL DP4<7:0>
addr. DATA OUT addr.
TRS TRDV
data
TRDQ
addr.
TWS
TDWL
TWDQ
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Publication Release Date: July 1998 Revision A1
W78C438C
TYPICAL APPLICATION CIRCUITS
Using 128K x 8 bit External EPROM (W27E010)
19999999999888888888 09876543210987654321 0 NP P C1 1 .. 43 NC NC NC NC P 1 . 2 P 1 . 1 P 1 . 0 D P 4 . 7 D P 4 . 6 D P 4 . 5 D P 4 . 4 D P 4 . 3 D P 4 . 2 D P 4 . 1 DVP P PD0 0 4D. . 01 . 0 P 0 . 2 PN 0C . 3 NC NC NC NC P0.4 P0.5 P0.6 P0.7 EA AP5.0 AP5.1 AP5.2 AP5.3
1 2
5V
10 U 8.2 K
3 4 5 P1.5 6 P1.6 7 P1.7 8 RESET 9 P8.0 10 11 12 13 14 15 16 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7
W78C438C
AP5.4 AP5.5 AP5.6 AP5.7 VDD VSS ALE PSEN P2.7 P2.6 P2.5 P2.4
17 INT3 18 INT2 19 P3.0, RXD 20 VDD 21 P3.1, TXD 22 P3.2, INT0 23 24 25 26 27 28 29 30 P3.3, INT1 P3.4, T0 P3.5, T1 P3.6, WR NC NC NC NC P 3 . 7XX , TT / A AV RL LS D2 1S 3333 1234
A P 7 . 3 , / C NS C3 33 56
A P 7 . 2 , / C S 2
A P 6 . 7 3334 7890
A P 7 . 1 , / C S 1
A P 7 . 0 , / C S 0
NC NC NC NC P2.3 51
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 GND 22 24
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE
O0 O1 O2 O3 O4 O5 O6 O7
13 14 15 17 18 19 20 21
W27E010
Vpp Vcc PGM 1 32 31
Vss
16
A P 6 . 6 4 1
A P 6 . 5
A P 6 . 4 44 23
A P 6 . 3 4 4
A P 6 . 2 4 5
A P 6 . 1 4 6
A P 6 . 0
P 2 . 0 44 78
P 2 . 1 4 9
P 2 . 2 5 0
R
C1
C2
Figure A
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W78C438C
CRYSTAL 16 MHz 24 MHz 33 MHz 40 MHz
C1 30P 15P 10P 5P
C2 30P 15P 10P 5P
R - - 6.8K 6.8K
Above table shows the reference values for crystal applications. Notes: 1. For C1, C2, R components refer to Figure A. 2. It is recommended that the crystals be replaced with oscillators for applications above 35 MHz.
PACKAGE DIMENSIONS
84-pin PLCC
HD D
11 1 84 75
12
74
Symbol
Dimension in inches
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.185 0.020 0.143 0.148 0.153 0.026 0.028 0.032 0.016 0.018 0.022 0.006 0.008 0.012 0.51 3.63 0.66 0.41 0.15 3.76 0.71 0.46 0.20 3.89 0.81 0.56 0.30 4.70
E
E HE
32
54
33
53
A A1 A2 b1 b c D E e GD GE HD HE L y
1.148 1.153 1.158 29.17 29.29 29.41 1.148 1.153 1.158 29.17 29.29 29.41 0.044 0.050 0.056 1.12 1.27 1.42 1.095 1.115 1.135 27.81 28.32 28.83 1.095 1.115 1.135 27.81 28.32 28.83 1.180 1.190 1.200 29.98 30.23 30.48 1.180 1.190 1.200 29.98 30.23 30.48 0.090 0.100 0.110 2.29 2.54 2.79 0.004 0 10 0 0.10 10
A2 A e Seating Plane y GD b A
Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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Publication Release Date: July 1998 Revision A1
W78C438C
Package Dimensions, continued
100-pin QFP
HD D
100 81
1
80
Symbol
Dimension in inches
Dimension in mm
Min. Nom.
0.004 0.107 0.010 0.004 0.546 0.782 0.020 0.728 0.964 0.039 0.087 0.112 0.012 0.006 0.551 0.787 0.026 0.740 0.976 0.047 0.095
Max.
0.130
Min. Nom.
0.10
Max.
3.30
E HE
30
51
A A1 A2 b c D E e HD HE L L1 y
Notes:
0.117 0.016 0.010 0.556 0.792 0.032 0.752 0.988 0.055 0.103 0.004
2.718 0.254 0.101 13.87 19.87 0.498 18.49 24.49 0.991 2.21
2.845 0.305 0.152 14.00 20.00 0.65 18.80 24.80 1.194 2.413
2.972 0.407 0.254 14.13 20.13 0.802 19.10 25.10 1.397 2.616 0.102
0
12
0
12
31
e
b
50
c
A2 A L L
1
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
See Detail F Seating Plane
A1 y
Detail F
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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